cy29948 2.5 v or 3.3 v, 200-mhz, 1:12 clock distribution buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07288 rev. *e revised may 2, 2011 2.5 v or 3.3 v, 200-mhz, 1:12 clock distribution buffer features 2.5 v or 3.3 v operation 200-mhz clock support lvpecl or lvcmos/lvttl clock input lvcmos-/lvttl-compatible inputs 12 clock outputs: drive up to 24 clock lines synchronous output enable output three-state control 150 ps typical output-to-output skew pin compatible with mpc948, mpc948l, mpc9448 available in commercial and industrial temp. range 32-pin tqfp package description the cy29948 is a low-voltage 200-mhz clock distribution buffer with the capability to select either a differential lvpecl or a lvcmos/lvttl compatible input clock. the two clock sources can be used to provide for a test clock as well as the primary system clock. all other cont rol inputs are lvcmos/lvttl compatible. the 12 outputs are lvcmos or lvttl compatible and can drive 50 ?? series or parallel terminated transmission lines. for series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:24. the outputs can also be three-stated via the three-state input ts#. low output-to-outp ut skews make the cy29948 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. the cy29948 also provides a synchronous output enable input for enabling or disabling the output clocks. since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. block diagram pecl_clk pecl_clk# 0 1 tclk tclk_sel sync_oe ts# vdd vddc 12 q0-q11 pin configuration cy29948 vss q0 vddc q1 vss q2 vddc q3 q11 vddc q10 vss q9 vddc q8 vss vss q4 vddc q5 vss q6 vddc q7 tclk_sel tclk pecl_clk pecl_clk# sync_oe ts# vdd vss 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 [+] feedback
cy29948 document number: 38-07288 rev. *e page 2 of 10 output enable/disable the cy29948 features a control input to enable or disable the ou tputs. this data is latched on the falling edge of the input cl ock. when sync_oe is asserted low, the outputs are disabled in a low st ate. when sync_oe is set high, t he outputs are enabled as shown in figure 1 . pin description [1] pin name pwr i/o description 3 pecl_clk ? i, pu pecl input clock 4 pecl_clk# ? i, pd pecl input clock 2 tclk ? i, pu external reference/test clock input 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 q(11:0) vddc o clock outputs 1 tclk_sel ? i, pu clock select input . when low, pecl clock is selected. when high tclk is selected. 5 sync_oe ? i, pu output enable input . when asserted high, the outputs are enabled. when set low the outputs are disabled in a low state. 6 ts# ? i, pu three-state control input . when asserted low, the output buffers are three-stated. when set high, the output buffers are enabled. 10, 14, 18, 22, 26, 30 vddc ? ? 2.5 v or 3.3 v power supply for output clock buffers 7vdd?? 2.5 v or 3.3 v power suppl y 8, 12, 16, 20, 24, 28, 32 vss ? ? common ground tclk sync_oe q figure 1. sync_oe timing diagram note 1. pd = internal pull-down, pu = internal pull-up. [+] feedback
cy29948 document number: 38-07288 rev. *e page 3 of 10 maximum ratings [2] maximum input voltage relative to v ss ............. v ss ? 0.3 v maximum input voltage relative to v dd ............. v dd + 0.3 v storage temperature ............................... ?65 c to + 150 c operating temperature............................... ?40 c to +85 c maximum esd protection............................................... 2 kv maximum power supply................................................ 5.5 v maximum input current ............. .............. .............. .... 20 ma this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). dc parameters v dd = v ddc = 3.3 v 10% or 2.5 v 5%, over the specified temperature range. parameter description conditions min typ max unit v il input low voltage v dd = 3.3 v, pecl_clk single ended 1.49 ? 1.825 v v dd = 2.5 v, pecl_clk single ended 1.10 ? 1.45 all other inputs v ss ?0.8 v ih input high voltage v dd = 3.3 v, pecl_clk single ended 2.135 ? 2.42 v v dd = 2.5 v, pecl_clk single ended 1.75 ? 2.0 all other inputs 2.0 ? v dd i il input low current [3] ? ? ?100 a i ih input high current [3] ??100 v pp peak-to-peak input voltage pecl_clk 300 ? 1000 mv v cmr common mode range [4] pecl_clk v dd = 3.3 v v dd ? 2.0 ? v dd ? 0.6 v v dd = 2.5 v v dd ? 1.2 ? v dd ? 0.6 v ol output low voltage [5] i ol = 20 ma ? ? 0.4 v v oh output high voltage [5] i oh = ?20 ma, v dd = 3.3 v 2.5 ? ? v i oh = ?20 ma, v dd = 2.5 v 1.8 ? ? i ddq quiescent supply current ? 5 7 ma i dd dynamic supply current v dd = 3.3 v, outputs @ 100 mhz, c l =30pf ?180?ma v dd = 3.3 v, outputs @ 160 mhz, c l =30pf ?270? v dd = 2.5 v, outputs @ 100 mhz, c l =30pf ?125? v dd = 2.5 v, outputs @ 160 mhz, c l =30pf ?190? z out output impedance v dd = 3.3 v 12 15 18 ? v dd = 2.5 v 14 18 22 c in input capacitance ? 4 ? pf notes 2. multiple supplies: the voltage on any input or i/o pin cannot exceed the powe r pin during power-up. power s upply sequencing is not required. 3. inputs have pull-up/pull-down resistors that effect input current. 4. the v cmr is the difference from the most positive side of the differ ential input signal. normal operation is obtained when the ?high? i nput is within the v cmr range and the input lies within the v pp specification. 5. driving series or parallel terminated 50 ? (or 50 ? to v dd /2) transmission lines. [+] feedback
cy29948 document number: 38-07288 rev. *e page 4 of 10 ac parameters [6] v dd = v ddc = 3.3 v 10% or 2.5 v 5%, ov er the specified operating range. parameter description conditions min typ max unit f max input frequency [7] v dd = 3.3 v ? ? 200 mhz v dd = 2.5 v ? ? 170 t pd pecl_clk to q delay [7] v dd = 3.3 v 4.0 ? 8.0 ns tclk to q delay [7] 4.4 ? 8.9 pecl_clk to q delay [7] v dd = 2.5 v 6.0 ? 10.0 tclk to q delay [7] 6.4 ? 10.9 f outdc output duty cycle [7, 8, 9] measured at v dd /2 45 ? 55 % t pzl , t pzh output enable time (all outputs) 2 ? 10 ns t plz , t phz output disable time (all outputs) 2 ? 10 ns t skew output-to-output skew [7, 9] ? 150 250 ps t skew(pp) part-to-part skew [10] pecl_clk to q ? ? 1.5 ns tclk to q ? ? 2.0 t s set-up time [7, 11] sync_oe to pecl_clk 1.0 ? ? ns sync_oe to tclk 0.0 ? ? t h hold time [7, 11] pecl_clk to sync_oe 0.0 ? ? ns tclk to sync_oe 1.0 ? ? t r /t f output clocks rise/fall time [9] 0.8 v to 2.0 v, v dd = 3.3 v 0.20 ? 1.0 ns 0.6 v to 1.8 v, v dd = 2.5 v 0.20 ? 1.3 pulse generator z = 50 ohm zo = 50 ohm vtt zo = 50 ohm vtt r t = 50 ohm r t = 50 ohm cy29948 dut figure 2. lvcmos_clk cy29948 test reference for v cc = 3.3 v and v cc = 2.5 v notes 6. parameters are guaranteed by design and characterization. not 100% tested in production. all parameters specified with loaded outputs. 7. outputs driving 50 ? transmission lines. 8. 50% input duty cycle. 9. see figure 2 and figure 3 on page 5 . 10. part-to-part skew at a given temperature and voltage. 11. setup and hold times are relative to the falling edge of the input clock. [+] feedback
cy29948 document number: 38-07288 rev. *e page 5 of 10 differential pulse generator z = 50 ohm zo = 50 ohm zo = 50 ohm vtt r t = 50 ohm cy29948 dut zo = 50 ohm r t = 50 ohm vtt figure 3. pecl_clk cy29948 test reference for v cc = 3.3 v and v cc = 2.5 v figure 4. propagation delay (t pd ) test reference t pd pecl_clk pecl_clk v pp q v cmr vcc gnd vcc /2 figure 5. lvcmos propagation delay (t pd ) test reference t pd lvcmos_clk q vcc gnd vcc /2 vcc gnd vcc /2 figure 6. output duty cycle (f outdc ) vcc gnd vcc /2 t p t0 dc = tp / t0 x 100% [+] feedback
cy29948 document number: 38-07288 rev. *e page 6 of 10 figure 7. output-to -output skew tsk(0) t sk(0) vcc gnd vcc /2 vcc gnd vcc /2 ordering information part number package type production flow CY29948AC 32-pin tqfp commercial, 0 c to +70 c CY29948ACt 32-pin tqfp - tape and reel commercial, 0 c to +70 c pb-free cy29948axc 32-pin tqfp commercial, 0 c to +70 c cy29948axct 32-pin tqfp - tape and reel commercial, 0 c to +70 c cy29948axi 32-pin tqfp industrial, ?40 c to +85 c cy29948axit 32-pin tqfp - tape and reel industrial, ?40 c to +85 c ordering code definitions t = tape and reel; blank = tube temperature: x = c or i c = commercial; i = industrial x = pb-free package: a = 32-pin tqfp device part number company id: cy = cypress 29948 cy a x t x [+] feedback
cy29948 document number: 38-07288 rev. *e page 7 of 10 package drawing and dimensions 51-85063 *c [+] feedback
cy29948 document number: 38-07288 rev. *e page 8 of 10 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor esd electrostatic discharge i/o input/output lvcmos low voltage complementary metal oxide semiconductor lvpecl low voltage positive emitter coupled logic lvttl low voltage transistor-transistor logic pll phase locked loop tqfp thin quad flat pack symbol unit of measure c degree celsius kv kilo volts mhz mega hertz a micro amperes ma milli amperes mm milli meter mv milli volts ns nano seconds ? ohms % percent pf pico farad ps pico seconds vvolts [+] feedback
cy29948 document number: 38-07288 rev. *e page 9 of 10 document revision history document title: cy29948, 2.5 v or 3.3 v, 200-mhz, 1:12 clock distribution buffer document number: 38-07288 rev. ecn no. submission date orig. of change description of change ** 111099 02/13/02 brk new datasheet *a 116782 08/14/02 hwt added commercial temperature range *b 122880 12/22/02 rbi added power up requirements to maximum ratings *c 428221 see ecn rgl added lead-free devices *d 2904731 04/05/10 cxq removed inactive part numbers - cy29948ai and cy29948ait. updated package diagram. *e 3246222 05/02/2011 cxq added ordering code definitions . added acronyms and units of measure . updated in new template. [+] feedback
document number: 38-07288 rev. *e revised may 2, 2011 page 10 of 10 all products and company names mentioned in this document may be the trademarks of their respective holders. cy29948 ? cypress semiconductor corporation, 2002-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback
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